Packet switching system

ABSTRACT

In a packet switch, a switch request allocation plan is generated by reducing the number of queue requests VOQ relating to each of one or both sets of ports I1 .IN, O1 .ON, by a value such that the number of requests relating to each member of the set or sets of ports is no greater than the number of requests (frame value F) that can be handled by the switch ( 10 ). This reduction may be individually done for each queue. Alternatively all queues relating to a given port, or to any port, may have their length reduced by a single value determined by the size of the longest queue. A further stage may then apply other allocation rules to allocate requests remaining unallocated by the previous stage.

This invention relates to packet switching systems (also known as cellswitching systems) for communications networks, in particular methodsfor allocating output switching requests for traffic from the inputs ofa packet switch to its outputs. Fixed data units (slots) for switchingare created by processing input packets as necessary or by any othermeans such as forecasting.

Input-buffered packet switches and routers offer potentially the highestavailable bandwidth for any given fabric and memory technology, but suchsystems require accurate scheduling to make the best use of thisbandwidth. In such a scheduling process the header of each incomingpacket is processed to identify its destination and the individualpackets are then buffered in corresponding input queues, one for eachpossible pairing of input port with output port (port pair). Thescheduling process itself then determines a permutation (a switchconfiguration or an input/output switch port assignment) in whichpackets from the input queues should be transmitted such that conflictsdo not occur, such as two packets from different inputs competing forthe same slot in the output ports.

On each cycle of, many scheduling algorithms check the occupancy of onlythe first queue position (head of line) from each queue, but some checkthe occupancy of a group of queue positions (known as “frames”) as thisis more efficient. A frame-based scheduler determines, in one process, aset of switch permutations (one permutation per slot duration) in thenext frame period (the processed/scheduled frame).

Scheduling is one of the most serious limiting factors in Input-Bufferedpacket switches. Scheduling generally consists of two sub-processes,namely matching (or arbitration), and time slot assignment (or switchfabric path-search). Matching is essentially the selection of packetsfrom the input queues to maximise throughput within the constraints offrame lengths within both input and output ports (the “no-overbooking”constraint). Time slot assignment is the generation of a set ofpermutations (switching matrix configurations) for routing the packets(slots) through the switch for each slot duration.

A suitable scheduling process must satisfy two conditions; firstly thematching process must ensure that a “no overbooking” criterion is metfor each input port and each output port (the “matching” problem). Inother words it must arrange that the number of packets to be handled byeach port (input and output), will not exceed the frame length (innumber of time-slots) during the duration of the frame: ideally itshould equal the frame length for each port, but this is not alwayspossible as will be explained. Secondly, the time-slot assignmentprocess must allocate all the matched requests for data units (timeslots) for switching (in each permutation) during the frame time period.The present invention relates to the matching step of the schedulingprocess, which will be described in more detail later, after thisoverview of the whole packet switching system.

The packets are transmitted along a circuit established through theswitch fabric according to a switching matrix (set of permutations)generated in the scheduling process just described. An output bufferingstage may be provided in the output line cards before the packets arelaunched into the output links.

Maximum Size and Maximum Weight bipartite graph matching algorithmsexist, which can theoretically achieve 100% throughput, but thecomplexity of their implementation makes them slow and their applicationunfeasible. However, although the Maximunm Weight and, in somecircumstances, also the Maximum Size algorithms may solve the schedulingproblem they are too complex to use on a per packet basis. There alsoexist more recent approaches based on Birkhoff and Von Neumann's requestmatrix decomposition, but these generate long delays and thus areinappropriate for real-time scheduling. Hence, iterative, heuristic,parallel algorithms such as the i-SLIP process [N. McKeown, “The i-SLIPscheduling algorithm for input-queued switches”. IEEE Transactions onNetworking, vol. 7, no. 2, April 1999] and the Frame-based process havebeen developed. These heuristic algorithms are faster but, in the natureof heuristic algorithms, they do not provide a rigorous solution.

The “i-SLIP” scheduling algorithm, is an example of one that may operateslot-by-slot, (i.e. with a frame length of a single data unit ortime-slot) but alternatively it may use a frame-based approach whereinput queues' occupancies are each checked once every F time-slots,where the value of F is greater than one: this interval of F timeslotsis known as a “frame”. The result of the scheduling process is a N×FSwitch Matrix C, where N is the number of the switch input ports, fromwhich switching configurations (set of permutations) are decided for thenext frame-switching time period. The content of each element c(i,s) ofthe matrix C is the Switch Fabric Output Port number to which the “s”thslot of the frame coming from the “i”th input port is to be routed. Notethat some elements in matrix C may be empty. Typically there are thesame number of output ports as there are input ports (N). This is alwayslikely to be the case unless there is a preponderance of one-waycommunications connections served by the switch.

The scheduling problem will now be described in more detail.

After the required output port of each incoming packet is identified, byprocessing the header or otherwise, the individual packets are bufferedin corresponding input queues depending on the particular requestedinput/output port pair (VOQ). In order to establish the number ofpackets (time-slots), a counter is established for each queue (VOQ).Referring to FIG. 1, which shows a typical switch system, the SwitchFabric 20 has N input ports 31 . . . 3N (labelled input I₁ to inputI_(N)) and N output ports (labelled output O₁ to output O_(N)). Theswitching is under the control of a scheduler 10. In respect of eachinput port “i” the scheduler 10 maintains N queues (one per Output port“j”), labelled VOQ_(i,j) in FIG. 1, in which data units (slots) destinedfor the respective output port are buffered. Therefore in total thereare N² Virtual Output queues, and N² counters.

The number of switching Requests, for each Input port/Output port pairare stored in an N×N Request Matrix R. Each element r(i,j) of thismatrix shows the total number of packets pending in the VOQ betweeninput port ‘i’ and output port ‘j’.

In the example to be described below with reference to FIG. 1, a switchfabric with N=4 is used for simplicity, but in a typical switch thevalue of N is a much larger number. A switching-time period (period forwhich permutations are decided) is for the duration of one frame (Fslots), which can be one or more slots. This means that the matrix R isupdated once per frame time-period (with the intention that as many aspossible of the packets represented therein, according to the maximumswitch capacity, will be switched during the following time period).$\begin{matrix}{{\begin{matrix}\frac{{{Outlets}\quad{‘j’}}->}{{Inlets}\quad\left. {‘i’}\downarrow \right.} & \begin{matrix}O_{1} & O_{2} & O_{3} & O_{4}\end{matrix} \\\begin{matrix}I_{1} \\I_{2} \\I_{3} \\I_{4}\end{matrix} & \begin{matrix}3 & 4 & 2 & 0 \\5 & 0 & 1 & 0 \\8 & 5 & 1 & 3 \\2 & 0 & 2 & 6\end{matrix}\end{matrix}\quad R} = \begin{pmatrix}3 & 4 & 2 & 0 \\5 & 0 & 1 & 0 \\8 & 5 & 1 & 3 \\2 & 0 & 2 & 6\end{pmatrix}} & (1)\end{matrix}$

Matrix (1) represents a Request Matrix that will be used in thisexample, which has no further purpose other than to illustrate thescheduling process. Note that the total number of buffered packets foreach port varies, in this example, between six (input 12 and also outputO₃) and eighteen (output O₁), and cannot therefore match the frame sizefor all ports. Therefore, either some packets will not be switched, (thedata either being discarded or held over to the next frame), or someslots will be unused as there are not enough packets to use them all. Ingeneral the frame size is predetermined or could vary for eachframe-period. Nonetheless it will be fixed for the duration of a framescheduling.

In the matching process, a number of packets “F” corresponding to theframe length, selected from packets buffered at each input port queueare checked for acceptance, to make sure that there is no overbooking ofthe input and output ports within the frame. An N×N “Accepted-RequestsMatrix” A is defined, whose elements a_(i,j) represent the number ofpacket switching requests that are accepted from input port ‘i’ destinedfor output port ‘j’ in the next time period. The two conditions thatensure no overbooking are simply:${{\sum\limits_{j = 1}^{N}\quad a_{i,j}} \leqq {F\quad{for}\quad{all}\quad i}},{{{and}{\sum\limits_{i = 1}^{N}\quad a_{i,j}}} \leqq {F\quad{for}\quad{all}\quad{j.}}}$

Packets destined for overbooked ports may be discarded, or they maycontinue to be queued for transmission in later frames, if accuracy ismore important than latency (delay time).

From the matrix R discussed above, the Matching process populates an N×NAccepted-Requests Matrix A. The values of the elements in this matrixare such that the switch input and output ports capacity is notexceeded, i.e. none of the row and column summations in this matrixexceeds F, which is the number of time slots (data units) that will beswitched during the following time period. Note that we can generalisethis definition to all Matching Algorithms, whether frame-based or not,saying for example that in a slot by slot process, such as the i-SLIPalgorithm, the value of F is unity.

Matrix A below is an illustrative solution to the problem for therequests matrix R from (1). With a switching fabric with N=4 and a framelength F=8, the total switch capacity is N×F time-slots per time-period,which in this example is 32. $\begin{matrix}{\begin{matrix}\frac{{{Outlets}\quad{‘j’}}->}{{Inlets}\quad\left. {‘i’}\downarrow \right.} & \begin{matrix}O_{1} & O_{2} & O_{3} & O_{4}\end{matrix} & {{Row} - \left. {Sums}\downarrow \right.} \\\begin{matrix}I_{1} \\I_{2} \\I_{3} \\I_{4}\end{matrix} & \begin{matrix}2 & 4 & 2 & 0 \\3 & 0 & 1 & 0 \\2 & 3 & 1 & 2 \\1 & 0 & 2 & 5\end{matrix} & \begin{matrix}8 \\4 \\8 \\8\end{matrix} \\{{{Column} - {Sums}}->} & \begin{matrix}8 & 7 & 6 & 7\end{matrix} & \begin{matrix}{{{Total}\quad{Sum}} = 28} \\{{N \times F} = 32}\end{matrix}\end{matrix}{A = \begin{pmatrix}2 & 4 & 2 & 0 \\3 & 0 & 1 & 0 \\2 & 3 & 1 & 2 \\1 & 0 & 2 & 5\end{pmatrix}}} & (2)\end{matrix}$

A Matching algorithm attempts to completely fill up the matrix A takingthe requests from matrix R, in such a way that the total switchingrequests for every input and output port does not exceed the value F(No-overbooking), and the total capacity of the Switch (N×F) isachieved. We see that the example shown here has not achieved fillingthe matrix A to the maximum switch capacity (32 requests), but only 28.In fact, because the input queues are not balanced, it is not possibleto fill the remaining four slots in this example.

The solution represented by illustrative matrix A could be achievedreasonably quickly by trial and error from the matrix R. However, inpractice switch fabrics have values for N (the number of ports) muchgreater than the illustrative value of 4 and a systematic approach isrequired. The present invention presents such an approach. Before theinvention is discussed, there follows a description of the subsequentstages in the process.

Usually, the Matching Algorithms only check the occupancy (by inspectingthe counters) of the first locations in each virtual output queue, orinput-output pair queue (heads of queues) to a maximum of F locationsper input port (i.e. all virtual queues corresponding to the same inputport), without taking into account all switching requests. There existsome Matching Algorithms that check the occupancy of a higher number ofqueue locations, for instance a multiple of the value of F. For example,if F=8, we could check occupancy in the first 16 locations (2F) in eachbacklogged input queue to try to completely populate theAccepted-Requests Matrix A.

On the other hand, some Matching Algorithms use a number of iterations.This means that part of the algorithm is run more than once, alwaysusing the same queue locations as in the first time. This usuallyimproves the filling ratio of the Accepted-Requests Matrix and thereforethe switching throughput. Examples include i-SLIP (i>1), or Framebasedalgorithms using some variants of the port pointer update rule [A.Bianco et al., “Frame-based scheduling algorithms for best-effort cellor packet switching”, Workshop on High Performance Switching andRouting, HPSR 2002, May 2002, Japan]. Different versions of theframe-based algorithm have different rules for updating the portpointers and some variants of the frame-based algorithm look twice atthe buffer occupancies on the same locations. For example, the versionsknown as NOB-27 and NOB-25 both use the same update rule but NOB-27 runspart of the process twice on the same buffer locations. Once theaccepted requests matrix A has been generated, the second sub-process inthe scheduling algorithm computes the set of switch permutations andassigns the time-slots within a frame to the accepted requests for eachone of the permutations. In this way the switch fabric can be configuredfor each time slot avoiding conflicts at the output ports, i.e. there isat most one packet from any input queue to one particular output port.This process can be referred to as Time Slot Assignment (TSA). From thematrix of accepted requests A, we build the NxF Switch Matrix C. Theelements c(i,s) of C show the output port number to which a switchingrequest in input port ‘i’ will be switched in the slot ‘s’ of the frameof length F that is being scheduled. There are a number of algorithms toachieve this, among them the one described in the applicant's existingpatent application W001/67802. Any particular packet should be capableof transmission across the switch fabric during any one of the timeslots in the frame, although normally packets from the same queue (thatis to say, between the same pair of ports) would be transmitted in thesame order that they had originally arrived at the input port.

For example, from the illustrative “accepted requests” matrix A found in(2) the Switch Matrix C shown in (3) might be generated. The columns ofmatrix C represent the time-slots. At each time-slot the switch fabrichas to be configured such that the packets present at the Input Portsare connected to the Output Port shown in each element c(i,s) of matrixC. $\begin{matrix}{\begin{matrix}\frac{{{Time} - {{slot}\quad{‘s’}}}->}{{Inlet}\quad\left. {‘i’}\downarrow \right.} & \begin{matrix}S_{1} & S_{2} & S_{3} & S_{4} & S_{5} & S_{6} & S_{7} & S_{8}\end{matrix} \\\begin{matrix}I_{1} \\I_{2} \\I_{3} \\I_{4}\end{matrix} & \begin{matrix}1 & 1 & 2 & 2 & 2 & 2 & 3 & 3 \\3 & \quad & 1 & \quad & 1 & \quad & \quad & 1 \\2 & 2 & 4 & 4 & 3 & 1 & 1 & 2 \\4 & 3 & 3 & 1 & 4 & 4 & 4 & 4\end{matrix}\end{matrix}{C = \begin{pmatrix}1 & 1 & 2 & 2 & 2 & 2 & 3 & 3 \\3 & \quad & 1 & \quad & 1 & \quad & \quad & 1 \\2 & 2 & 4 & 4 & 3 & 1 & 1 & 2 \\4 & 3 & 3 & 1 & 4 & 4 & 4 & 4\end{pmatrix}}} & (3)\end{matrix}$

Therefore matrix C shows a set of possible switch fabric configurationsfor an entire frame period. Each column of matrix C shows a switchpermutation with no output port conflicts, i.e., no column of matrix Ccontains more than one occurrence of any output port number. The matrixC is the final result of the entire scheduling problem. Note that wherethe frame size F=1, as for the “i-SLIP” algorithm, matrix C is a columnvector (N×1 matrix), and therefore the time-slot scheduling algorithm isstraightforward.

An output memory stage may be provided where the slots could bere-sequenced (re-ordering and/or closing gaps between slots belonging tothe same original packet).

Scheduling is therefore made up of the matching problem, and the timeslot assignment problem. In the matching problem switching requests areaccepted in such a way that the switching capacity is not exceeded whileachieving maximum throughput. The assignment problem selects a set ofswitch fabric configurations (permutations) within the frame-length.This has known exact solutions at acceptable complexities. However, someissues might arise due to slot sequencing that could lead to thenecessity for an output memory stage where slots could be re-sequenced.

Although some hitherto known heuristic matching algorithms generallyperform well, there are some situations in which their performancedeteriorates, in particular with unbalanced traffic patterns and burstytraffic sources. The consequences are that these matching algorithms areunable to ensure the ideal 100% throughput, and therefore some packetswill be dropped (lost). This type of situation is becoming increasinglysignificant, as it is foreseen that the network churn (traffic patterns)will become highly dynamic, and not predictable.

The performance degradation occurs because these algorithms check thequeues' occupancy only within a limited number of locations in the inputqueues. Therefore when a particular input queue backlog keeps growingthese algorithms do not necessarily serve it because they are unaware ofsuch condition. This leads to inefficiency becoming apparent at hightraffic loads for highly unbalanced traffic patterns, that is, when thenumber of packets requesting to be switched for one particular or moreinput-output port pairs is much higher than for the others. This iscommon to many prior art heuristic matching algorithms as this processonly scan the occupancy of a specified limited number of locations inthe backlogged input queues, eventually leading to some packets beingprocessed too late in certain traffic conditions.

One aspect of the present invention seeks to overcome this weakness bysplitting the problem into a number of stages. Another aspect applies atransformation process to the switching request matrix, factorising itwith respect to the switch port capacities. Although this transformationprocess could be used on its own, it is preferably used as the initialstage of two or more stages according to the first aspect.

According to the present invention there is provided a method ofallocating switch requests within a packet switch, the method comprisingthe steps of

-   -   (a) generating switch request data for each input port        indicative of the output ports to which data packets are to be        transmitted    -   (b) processing the switch request data for each input port to        generate request data for each input port-output port pairing;        and    -   (c) generating an allocation plan for the switch for a frame of        a defined number of packets, by a first stage in which        allocation rules are applied such that the number of requests        from each input port and to each output port is no greater than        the defined frame length, and one or more further stages in        which allocation rules are applied to allocate requests        remaining unallocated by the previous stage.

Each stage attempts a complete solution to maximising allocations, usingthe unallocated requests remaining from the previous stage. The stagesmay use the same or different allocation rules. Some of stages mayarrive at their complete solutions by an iterative process, such as theNOB-27 process already referred to.

One of the stages may be a method according to the applicant'sco-pending International application, having the same filing date as thepresent application and applicant's reference A30169WO, claimingpriority from United Kingdom applications 0218565.0 and 0228917.1. Thismethod comprises the steps of

-   -   (a) generating switch request data for each input port        indicative of the output ports to which data packets are to be        transmitted;    -   (b) processing the switch request data for each input port to        generate request data for each input port-output port pairing;        and    -   (c) generating an allocation plan by reducing the number of        queue requests relating to each of one or both sets of ports by        a value such that the number of requests relating to each member        of the set or sets of ports is no greater than a predetermined        frame value.

The transformation of the request data may be done by summing up theswitching requests from each input port, or the switching requests toeach output port, or both, and reducing the number of requests from eachinput port, and to each output port, in such cases where the number ofrequests is greater than the maximum capacity of the relevant port, by afactor selected such that the total number of requests from thecorresponding input port or to the corresponding output port is nogreater than the maximum capacity of the corresponding input port andthe corresponding output port. Thus the queue with the greatest numberof switching requests is identified and served so as to keep the packetswitch in a stable state for any possible traffic pattern, provided thetraffic is admissible, i.e., the average switch request rate to anyoutput port does not exceed the line rate of that output port (thiscondition applies to any scheduling algorithm). This invention allowsthe matching process to achieve maximum possible throughput for anyinput traffic statistics and with any traffic pattern, at a lowcomplexity.

The reduction of the request data may comprise reducing the number ofrequests in the input ports; and then reducing the number of requests inthe resulting transformed request data where it still exceeds thecapacity of the output ports. Alternatively the output ports may beconsidered before the input ports.

Alternatively, the reduction of the request data from each input portand to each output port may be done using a common factor selected suchthat the number of requests from each input port and to each output portis no greater than the maximum capacity of either port. This process isquicker, but may lose some possible allocations.

This process ensures that all queued requests are considered, and iscomputationally simple, and therefore relatively fast. However, it mayleave some capacity unfilled and/or cause unnecessary delays. It ispreferably followed by one or more other allocation processes to fillany remaining capacity.

Unallocated switch requests may be reserved for use in the next stage ofswitch request allocation, or abandoned if they have an expiry time.

The invention extends to a method of packet switching wherein thepackets are switched on the basis of the allocated routing, and to apacket switch in which the input port-output port routing is allocatedin accordance with the method of the invention, and packets are switchedfrom an input port to a specified output port in accordance with theallocated routing.

An embodiment of the invention will now be described, by way of example,with reference to the drawings, in which

FIG. 1, which has already been discussed, illustrates a simplifiedpacket switching system,

FIG. 2 is a graph comparing the performance of the i-slip algorithm, aframe-based algorithm using the NOB25 pointer update rule as describedin an earlier patent application of the applicant (W001/67803), and atwo-stage process according to the first aspect of the invention. Thefirst stage of this two-stage process comprises request data reductionprocess using a common factor, according to the second aspect of thepresent invention. The second stage is the frame-based algorithm (NOB25)also used in the earlier patent application.

The matching process according to the present invention applies multiplestages. Traditional heuristic matching processes (e.g. i-SLIP andFrame-based) find matrix A directly from R,R

A

The reduction of request data of the second aspect of the invention canbe used on its own, but preferably precedes a heuristic matchingalgorithm, in general partially populating matrix A. In such a two-stageprocess, the original request matrix R₀=R is transformed to find a“normalised matrix” R_(norm), in which the capacities of the input andoutput ports are not exceeded, and a “remaining request” matrix R₁,where R₁=R₀−R_(norm). The matrix R_(norm), is used to start to populatethe Accepted-Requests Matrix A. The partially populated matrix will bereferred to as A⁻.A⁻≡R_(norm)

Now, to fill up the remaining capacity in the matrix A, it is necessaryto use another matching algorithm. We could call this A⁺ matrix,R₁

A⁺

Now,A=A⁻+A⁺

The matching matrix A is the sum of the two matrices found during atwo-stage example of the present invention. A request matrixtransformation may be applied to either stage, (preferably the first)applying to the second stage any other known matching algorithm, or itmay be applied to both the first and second stages.

In general, the transformation presented here will precede theapplication of other matching algorithms.

Note that this splitting process can be reiterative in more than twostages, in each stage applying any transformation of this invention orany other known matching algorithm.

An example of the process of generating the transformed matrix, referredto herein as “Normalisation1”, and the subsequent stages, will now bediscussed, using an exemplary Request matrix: Outlets ‘j’ Inlets ‘i’ O₁O₂ O₃ O₄ Row - Sums I₁ 3 4 2 0 9 I₂ 5 0 1 0 6 I₃ 8 5 1 3 17 I₄ 2 0 2 610 Column - Sums → 18 9 6 9 Highest sum mval = 18

In this example there are, as before, four input ports and four outputports, and the frame length F is again 8. A value mval is derived fromthis matrix, which is the largest sum of any column or any row in thematrix, which in this case is the total number of requests for outputport 1.

The process requires the transformation of the request matrix R₀ to finda matrix R_(norm), in which the capacities of the input and output portsare not exceeded. The result is used to generate the partially filledmatrix A⁻. The transformation performed in this example uses a commonfactor d=F/max(F, mval), which in the case of this example is d=8/18 or0.44. In other words, if the number of requests in respect of anyport-input or output-(mval) is greater than the frame length, the valueof every term in the matrix is reduced by a factor such that the totalnumber of requests in respect of that port is equal to, or less than,the frame length. $R_{0} = {\left. \begin{pmatrix}3 & 4 & 2 & 0 \\5 & 0 & 1 & 0 \\8 & 5 & 1 & 3 \\2 & 0 & 2 & 6\end{pmatrix}\Rightarrow R_{norm} \right. = {\left\lfloor {\frac{8}{18}R_{0}} \right\rfloor = {\begin{pmatrix}1 & 1 & 0 & 0 \\2 & 0 & 0 & 0 \\3 & 2 & 0 & 1 \\0 & 0 & 0 & 2\end{pmatrix} = A^{-}}}}$and the remaining Request Matrix is$R_{1} = {R_{0} = {R_{norm} = \begin{pmatrix}2 & 3 & 2 & 0 \\3 & 0 & 1 & 0 \\5 & 3 & 1 & 2 \\2 & 0 & 2 & 4\end{pmatrix}}}$

It will be seen that matrix A is not full yet. The remaining capacity inmatrix A can then be filled using the updated matrix R₁ and for examplethe known Frame based algorithm of the applicant's existingInternational Patent Application W001/67803 using the pointer updaterule NOB25, or the process described in the applicant's Internationalpatent application filed on the same date as the present case, havingapplicant's reference A30137WO and claiming priority from United KingdomPatent Applications 0218565.0 and 0228903.1.

Further refinements of the invention will now be described.

The process “Normalisation 1” described above does not completelypopulate the matrix A, because of the generalisation of ‘mval’ to allelements in the matrix R₀. As a result, some Inlet-Outlet pairs in theR₀ matrix are not heavily loaded, and therefore could be allowed asmaller ‘mval’, i.e., a bigger transforming factor.

Limiting each column total to the frame length ensures that the “nooverbooking” condition is met for each Output Port. Similarly, limitingeach row total to the frame length analogously ensures “no overbooking”of all input ports. The following variant embodiment generates aseparate value ‘mval’ for each term in the matrix, being the highest ofthree values: the respective totals for the row and column of which thatterm is a member, and the frame length. We therefore have a set ofnormalising factors that may be different for each element of matrix R₀.We arrange this set in a matrix form. This transformation is referred toherein as “Normalisation2”. $\left. \begin{matrix}\frac{{{Outlets}\quad{‘j’}}->}{{Inlets}\quad\left. {‘i’}\downarrow \right.} & \begin{matrix}O_{1} & O_{2} & O_{3} & O_{4}\end{matrix} & {{Row} - \left. {Sums}\downarrow \right.} \\\begin{matrix}I_{1} \\I_{2} \\I_{3} \\I_{4}\end{matrix} & \begin{matrix}3 & 4 & 2 & 0 \\5 & 0 & 1 & 0 \\8 & 5 & 1 & 3 \\2 & 0 & 2 & 6\end{matrix} & \begin{matrix}9 \\6 \\17 \\10\end{matrix} \\{{{Column} - {Sums}}->} & \begin{matrix}18 & 9 & 6 & 9\end{matrix} & \quad\end{matrix}\Rightarrow{mval} \right. = \begin{pmatrix}18 & 9 & 9 & 9 \\18 & 9 & 6 & 9 \\18 & 17 & 17 & 17 \\18 & 10 & 10 & 10\end{pmatrix}$In order to find each element r_(norm ij) of the normalised matrixR_(norm) we have$r_{{norm}\quad{ij}} = \left\lfloor {r_{0\quad{ij}} \cdot \frac{F}{\max\left( {F,{mval}_{ij}} \right)}} \right\rfloor$where r_(oij) represent each element of the request matrix Rot andmival_(ij) represent each element of the matrix mval. This operationresults in the following normalised matrix $R_{norm} = {\begin{pmatrix}1 & 3 & 1 & 0 \\2 & 0 & 1 & 0 \\3 & 2 & 0 & 1 \\0 & 0 & 1 & 4\end{pmatrix} = A^{-}}$

It will be seen that in this particular example the highest summation(‘mval’) is that for column O₁, namely 18, and so all terms in the firstcolumn of the matrix are multiplied by 8/18=0.44 (all decimal figuresapproximated to two places). The next highest summation is in row I₃(mval=17), so all terms in row I₃, except the first, are multiplied by8/17=0.47. Similarly all terms in row 14 except the first are multipliedby 8/10=0.8, the remaining terms in row I₁ and columns O₂ and O₄ are all8/9=0.89. Finally, Row I₂ and column O₃ both have an ‘mval’ of 6, whichis less than the frame length, so the term at the intersection of thatrow and column takes the value of unity (not 8/6).

The Remaining Switch Request Matrix R₁ is then determined as:$R_{1} = {{R_{0} - R_{norm}} = \begin{pmatrix}2 & 1 & 1 & 0 \\3 & 0 & 0 & 0 \\5 & 3 & 1 & 2 \\2 & 0 & 1 & 2\end{pmatrix}}$

In this case, we have been able to populate matrix A more densely thanusing the “Normalisation 1” process described above, leaving lesswork-load for the following stage. However, there is added complexity asnow we need N² registers to store the ‘inmal’ matrix, instead of asingle value.

A further development, referred to herein as “Normalisation3” consistsin including a further phase (or step) and simplifying the first onewithin the transformation process. In this embodiment, the matrix R₀ istransformed using a vector in a first step and in a second steptransforming only one of the ports. The vector can be derived from the‘mvial’ of each individual row or, as shown below, each individualcolumn, but otherwise follows the same procedure as previouslydescribed. $\left. \begin{matrix}\frac{{{Outlets}\quad{‘j’}}->}{{Inlets}\quad\left. {‘i’}\downarrow \right.} & \begin{matrix}O_{1} & O_{2} & O_{3} & O_{4}\end{matrix} & \quad \\\begin{matrix}I_{1} \\I_{2} \\I_{3} \\I_{4}\end{matrix} & \begin{matrix}3 & 4 & 2 & 0 \\5 & 0 & 1 & 0 \\8 & 5 & 1 & 3 \\2 & 0 & 2 & 6\end{matrix} & \quad \\{{{Column} - {Sums}}->} & \begin{matrix}18 & 9 & 6 & 9\end{matrix} & \quad\end{matrix}\Rightarrow{mval}^{1} \right. = \begin{pmatrix}18 & 9 & 6 & 9\end{pmatrix}$$r_{{norm}\quad{ij}}^{1} = \left\lfloor {r_{0\quad{ij}} \cdot \frac{F}{\max\left( {F,{mval}_{j}^{1}} \right)}} \right\rfloor$where r_(0ij) represent the element in row i and column j of the requestmatrix R₀, and mval_(j) ¹ represent each element of the vector mval¹, jbeing the same value taken for the element r_(0ij). Therefore eachmatrix element r_(0ij) belonging to the same column j will be normalisedusing the same factor resulting from F/max(F, mval_(j) ¹). Thisoperation results in the first normalised matrix of the process that is$R_{norm}^{1} = \begin{pmatrix}1 & 3 & 2 & 0 \\2 & 0 & 1 & 0 \\3 & 4 & 1 & 2 \\0 & 0 & 2 & 5\end{pmatrix}$

After this first step is finished, the second step considers eachindividual column or row, whichever was not done in the first step. Anyof these which exceed the maximum capacity are transformed again, butthey are otherwise left as they are. In this example, it can be seenfrom inspection of the third row of R_(norm) ¹ that the request sum forinput port 3 is still higher than the port capacity F: Outlets ‘j’Inlets ‘i’ O₁ O₂ O₃ O₄ Row - Sums R_(norm) ¹ = I₁ 1 3 2 0 6 I₂ 2 0 1 0 3I₃ 3 4 1 2 10 > F I₄ 0 0 2 5 7 Column - Sums → 6 7 6 7From the matrix R_(norm) ¹ we can find again a vector with the summingof each matrix row. ThereforeR _(norm) ¹ mval ²=(6 3 10 7)Now we can apply again the normalisation, that is$r_{{norm}\quad{ij}}^{2} = \left\lfloor {r_{{norm}\quad{ij}}^{1} \cdot \frac{F}{\max\left( {F,{mval}_{i}^{2}} \right)}} \right\rfloor$where r_(norm ij) ¹ represent the element in row i and column j of therequest matrix R_(norm) ¹, and mval_(i) ² represent each element of thevector nzval², i being the same value taken for the element r_(norm ij)¹. Hence each matrix element r_(norm ij) ¹ belonging to the same row iwill be normalised using the same factor resulting from F/max(F,mval_(i) ²). Therefore we perform a further step in this stage, in whichonly the requests in the port where they exceed F (port capacity) arenormalised by a factor F/mval_(i) ²=8/10 (note that in this particularcase i=3), remaining the rest of the elements unchanged. This operationresults in the second and final normalised matrix of the process that is$R_{norm}^{2} = {\begin{pmatrix}1 & 3 & 2 & 0 \\2 & 0 & 1 & 0 \\2 & 3 & 0 & 1 \\0 & 0 & 2 & 5\end{pmatrix} = A^{-}}$$R_{1} = {{R_{0} - R_{norm}^{2}} = {\begin{pmatrix}2 & 1 & 0 & 0 \\3 & 0 & 0 & 0 \\5 & 2 & 0 & 2 \\2 & 0 & 0 & 1\end{pmatrix}{Remaining}\quad{Switch}\quad{Request}\quad{Matrix}}}$

This algorithm can also be started using the Input requests summations,and reducing the output requests in the second stage, instead of theother way round as described above.

Instead of reducing each value in a row or column by a common factor, acommon value could instead be subtracted. FIG. 2 shows a comparison ofthe mean packet delay for three processes:

-   1. a prior art system known as i-SLIP with 3 iterations, labelled    3-SLIP in the figure,-   2. the prior art Frame-based matching algorithm (W001/67803)    previously discussed, using the pointer update rule NOB25, labelled    NOB25 in the Figure.-   3. the present invention, labelled NOBITO in the figure, using a    Normalisation process similar to Normalisation 2, except that a    single mval, equal to the largest sum of any row or column, was used    for all terms in the matrixin the first stage and the same prior art    Frame-based matching algorithm (with pointer update rule NOB25) as a    second stage.

The Frame-based matching algorithm was run using one iteration and a 32time-slot duration frame in all cases. The scenario is a 8×8 switch,using bursty packet arrivals with a mean burst duration of 256 packets,and with a traffic matrix P, in which element P(i,j) indicates theprobable level of traffic between input port “i” and output port “j”:$P = {\frac{1}{255}\begin{pmatrix}1 & 2 & 4 & 8 & 16 & 32 & 64 & 128 \\2 & 4 & 8 & 16 & 32 & 64 & 128 & 1 \\4 & 8 & 16 & 32 & 64 & 128 & 1 & 2 \\8 & 16 & 32 & 64 & 128 & 1 & 2 & 4 \\16 & 32 & 64 & 128 & 1 & 2 & 4 & 8 \\32 & 64 & 128 & 1 & 2 & 4 & 8 & 16 \\64 & 128 & 1 & 2 & 4 & 8 & 16 & 32 \\128 & 1 & 2 & 4 & 8 & 16 & 32 & 64\end{pmatrix}}$

The results of FIG. 2 are for the links represented by the antidiagonalterms of this matrix.

FIG. 2 shows that the prior art systems are only capable of achieving a90% throughout, while using the present embodiment it is able to achieve100% throughput. Because the buffer lengths have to be finite, packetsare dropped (lost) from the queues when they reach a maximum delay. Thisis shown in the graph, where the curves become horizontal.

Therefore, the invention shows all advantages of the i-SLIP andframe-based algorithms and dramatically improves the performance at hightraffic loads for any type of traffic sources and traffic patterns.Following the first stage of the process, the second stage of thematching problem deals with the remaining request matrix filling in therest of the slot switch capacity, using for example a single iterationof a frame-based algorithm.

Table 1 below presents a number of examples of the use of the presentinvention. Two different normalisation methods according to the presentinvention are compared. Normalisation method 3 assigns a separate ‘mval’in the row and column for each r_(i,j) matrix entry. This means thatsome matrix entries could be rounded down twice. By normaliation 2assigns the larger of the row and column ‘mval’ for each matrix entry.By assigning only one ‘mval’ to each matrix entry, each one is onlyrounded down once.

For the second stage, data is shown for three different variants: eitherof those disclosed in the applicant's co-pending applications A30137referred to above, or W001/67803, (the latter using the NOB-25 rule) oranother algorithm known as “Ring” which was proposed by Politecnico diTorino within the European Union's collaborative project DAVID[“Description of Network Concepts and Frame of the Work”, DAVID(IST-1999-11742) project Deliverable D11, March 2002]. This ‘Ring’algorithm is a greedy maximal approximation of a maximum weight matching[R. E. Tarjan, “Data Structures and Network Algorithms”, Society forIndustrial and Applied Mathematics, November 1983], a well known problemin graph theory.

Data is also shown for a single stage process, and for processes havingtwo similar stages.

The resulting Accepted-Requests Matrices A for each combination shown inTable 1 are shown in Table 2. In this example it is seen that theexamples using a preliminary stage of the normalisation process 2(examples d,e, and f) and Normalisation Process 3 (examples g, h, and l)of the present invention provide a higher filling cardinality than thosewhich do not. Of those, the Frame-based algorithm (using NOB25 rule)process (examples f and i) generate a larger number of filled requests,(up to 28) but the filled matrices of the “Ring” process, (examples dand g) and of our co-pending application A30137 referred to above(examples e and h) provide a better match to the proportions of theoriginal Request matrix R₀, i.e., closer to a maximum weight matching.TABLE 1 Comparison of different combinations of algorithms in atwo-stage implementation of the present invention. Cardinality Stage 1Stage 2 (No of Accepted Requests) a) (No first stage) A30137 23 b) RingRing 25 c) A30137 A30137 23 d) Normalisation2 Ring 26 e) Normalisation2A30137 26 f) Normalisation2 WO01/67803 28 g) Normalisation3 Ring 27 h)Normalisation3 A30137 27 i) Normalisation3 WO01/67803 28

TABLE 2 Accepted-Requests Matrices, using the different combinations ofTable 1. A = $\begin{matrix}\left. a \right) \\\begin{bmatrix}0 & 4 & 2 & 0 \\0 & 0 & 1 & 0 \\8 & 0 & 0 & 0 \\0 & 0 & 2 & 6\end{bmatrix}\end{matrix}\quad$ $\begin{matrix}\left. b \right) \\\begin{bmatrix}0 & 4 & 2 & 0 \\2 & 0 & 1 & 0 \\6 & 2 & 0 & 0 \\0 & 0 & 2 & 6\end{bmatrix}\end{matrix}\quad$ $\begin{matrix}\left. c \right) \\\begin{bmatrix}0 & 4 & 2 & 0 \\0 & 0 & 1 & 0 \\8 & 0 & 0 & 0 \\0 & 0 & 2 & 6\end{bmatrix}\end{matrix}\quad$ $\begin{matrix}\left. d \right) \\\begin{bmatrix}1 & 4 & 2 & 0 \\2 & 0 & 1 & 0 \\5 & 2 & 0 & 1 \\0 & 0 & 2 & 6\end{bmatrix}\end{matrix}\quad$ $\begin{matrix}\left. e \right) \\\begin{bmatrix}1 & 4 & 2 & 0 \\2 & 0 & 1 & 0 \\5 & 2 & 0 & 1 \\0 & 0 & 2 & 6\end{bmatrix}\end{matrix}\quad$ $\begin{matrix}\left. f \right) \\\begin{bmatrix}2 & 4 & 2 & 0 \\3 & 0 & 1 & 0 \\3 & 2 & 1 & 2 \\0 & 0 & 2 & 6\end{bmatrix}\end{matrix}\quad$ $\begin{matrix}\left. g \right) \\\begin{bmatrix}1 & 4 & 2 & 0 \\3 & 0 & 1 & 0 \\4 & 3 & 0 & 1 \\0 & 0 & 2 & 6\end{bmatrix}\end{matrix}\quad$ $\begin{matrix}\left. h \right) \\\begin{bmatrix}1 & 4 & 2 & 0 \\3 & 0 & 1 & 0 \\4 & 3 & 0 & 1 \\0 & 0 & 2 & 6\end{bmatrix}\end{matrix}\quad$ $\begin{matrix}\left. g \right) \\\begin{bmatrix}2 & 4 & 2 & 0 \\3 & 0 & 1 & 0 \\2 & 3 & 1 & 2 \\0 & 0 & 2 & 6\end{bmatrix}\end{matrix}\quad$

1. A method of allocating switch requests within a packet switch, themethod comprising the steps of (a) generating switch request data foreach input port indicative of the output ports to which data packets areto be transmitted; (b) processing the switch request data for each inputport to generate request data for each input port-output port pairing;(c) generating an allocation plan for the switch for a frame of adefined number of packets, by a first stage in which allocation rulesare applied such that the number of requests from each input port and toeach output port is no greater than the defined frame length, and one ormore further stages in which allocation rules are applied to allocaterequests remaining unallocated by the previous stage.
 2. A methodaccording to claim 1, wherein unallocated switch requests are reservedfor use in a subsequent stage of switch request allocation.
 3. A methodaccording to claim 1, wherein at least one of the stages is a processcomprises the steps of (a) generating switch request data for each inputport indicative of the output ports to which data packets are to betransmitted; (b) processing the switch request data for each input portto generate request data for each input port-output port pairing; (c)generating an allocation plan by reducing the number of queue requestsrelating to each of one or both sets of ports by a value such that thenumber of requests relating to each member of the set or sets of portsis no greater than a predetermined frame value.
 4. A method according toclaim 3, wherein the transformation of the request data is done by usingthe summations of the requests from each input port.
 5. A methodaccording to claim 3, wherein the transformation of the request data isdone by using the summations of the requests to each output port.
 6. Amethod according to claim 3, wherein the reduction of the request datafrom each input port and to each output port is done, in such caseswhere the number or requests is greater than the maximum capacity of thecorresponding input port or corresponding output port, the reductionbeing by a factor selected such that the number of requests from thecorresponding input port and to the corresponding output port is nogreater than the maximum capacity of the corresponding input port andthe corresponding output port.
 7. A method according to claim 3, whereinthe reduction of the request data from each input port and to eachoutput port is done using a common factor selected such that the numberof requests from each input port and to each output port is no greaterthan the maximum request capacity of each input port and each outputport.
 8. A method according to claim 3, wherein the reduction of therequest data comprises (a) reducing the number of requests to eachoutput port; and (b) reducing the number of requests in the resultingreduced request data that exceeds the capacity of each input port.
 9. Amethod according to claim 3, wherein the transformation of the requestdata comprises (a) reducing the number of requests from each input port;and (b) reducing the number of requests in the resulting reduced requestdata that exceeds the capacity of each output port.
 10. A methodaccording to claim 3, wherein the process is iterative, and is repeatedone or more times in respect of input ports and output ports for whichcapacity remains available after the previous iteration is complete. 11.A method of packet switching wherein the input port-output port routingis allocated according to the method of claim 1 and the packets areswitched on the basis of the allocated routing.
 12. A packet switch inwhich the input port-output port routing is allocated in accordance withthe method of claim
 1. 13. A packet switch according to claim 12,wherein packets are switched from an input port to a specified outputport in accordance with the allocated routing.